1. Field of the Invention
The present invention relates to a memory device with cell arrays arranged in a three-dimensional manner, and in particular, to a method of selecting cell array layers to reduce the effects of defective cells.
2. Description of the Related Art
Resistance RAM (ReRAM), which changes the resistance state of material with voltage, current, heat, etc., and utilizes the resistance state as data, has gained increasing attention as a likely candidate for replacing NAND-type flash memory (see, for example, Y. Hosoi et al, “High Speed Unipolar Switching Resistance RAM (RRAM) Technology” IEEE International Electron Devices Meeting 2006 Technical Digest p. 793-796). The resistance RAM seems to offer a high availability as large capacity file memory from the viewpoint of its suitability for refinement and lamination, while enabling configuration of cross-point cells.
However, in order to allow for lamination of a large number of cell arrays, the selection scheme is important for selecting a layer to which a selected memory cell belongs. This is because, inmost cases, the cell arrays are configured as cross-point cell arrays and signal wirings (such as access signal lines or data lines) for selecting cells are shared between layers, which could result in the effects of leakage current in defective cells encountered across different layers. If the effects of leakage current are pervasive, this may result in malfunction or increased power consumption. Consequently, this may reduce the effects of larger capacity obtained by the multi-layer configuration.
In addition, in order to achieve a simpler structure in a connection portion between wirings extended from the laminated cell array layers and circuits on a base substrate, it is important to share a signal wiring between layers. However, it is necessary to optimize the limitation of the effects of defective cells in relation to the sharing of the signal wirings.